1. Field of the Invention
The present invention relates to an apparatus for feeding a digital signal synchronized with a phase of an a.c. power supply.
2. Description of the Prior Art
In order to control a thyristor leonard system and a cyclo-converter which are capable of performing control of the phase for voltage adjustment or a power source system for recovering power, the system having a pulse width modulation system converter provided with a self-quenchable switching element, a control system for those systems, in general, requires a signal synchronized with a phase of the d.c. power supply so that the control system works in synchronization with the phase of an a.c. power supply.
With recent remarkable developments in microcomputers, microcomputers have been widely used in phase control units of thyristors as well as other control units.
To detect a phase-synchronized signal for a microcomputer, therefore, various kinds of phase locked loop circuits have been made practically available.
FIG. 1 shows an arrangement of a representative phase locked loop circuit.
As shown, a voltage detector 1 steps down a supply voltage and outputs phase voltage signals U, V, W to a logic detector circuit 2. The logic detector circuit 2 serves to transform the voltage signals U, V, W into a logic level "1" or "0" depending on the polarity of each signal and to feed logic signals 2a to 2c to a ROM 3 in which those logic signals 2a to 2c are applied, to lower rank addresses A0 to A2 of the ROM 2. The upper rank addresses A3 to A6 of the ROM 3 receive frequency-divided signals 7a to 7d sent from a frequency divider circuit 7. The ROM 3 stores pieces of binary voltage information 3a to 3c at the addresses corresponding to those address signals. Each binary voltage information 3a to 3c is read from a data output terminal D0 to D2 of the ROM 3 and is provided to an adder 4. The ROM 3 has the other data output terminal D3 from which a frequency-division clearing signal 3d is read, and is provided to the frequency dividing circuit 7. This clearing signal 3d serves to limit the division of an electric angle 180.degree. into 12 partial frequencies. The adder 4 serves to add the corresponding voltage signal to each binary voltage information 3a to 3c and provided the added signal 4a to a voltage smoothing circuit 5. The voltage smoothing circuit 5 serves to smooth the added signal 4a and feed a smoothed voltage signal 5a to a voltage oscillation circuit 6. The voltage oscillation circuit 6 transforms the smoothed voltage signal 5a into the corresponding pulse frequency signal 6a, for example, a frequency corresponding to 12-fold power frequency f.sub.s. The frequency divider circuit 7 divides the pulse signal 6a into divided frequency signals 7a to 7d of 1/16, 1/8, 1/4 and 1/2.
In the case where no voltage abnormality or no phase slippage appears in the a.c. power source, the ROM 3 specifies each binary data stored at each phase interval 15.degree. (180.degree./120 to the corresponding address so that the ROM 3 may output a voltage signal 3a of "1" at a first 90.degree. interval (0.degree. to 90.degree.), a signal 3a of "0" at a second 90.degree. interval (90.degree. to 180.degree.), a signal 3a of "1" at a third 90.degree. interval (180.degree. to 270.degree.), and a signal 3a of "0" at a fourth 90.degree. interval (270.degree. to 360.degree.) and voltage signals 3b, 3c for the other two phases (V and W phases) at the data output terminals D0, D1, D2. The voltage signals 3b and 3c are respectively shifted by 120.degree. and 240.degree. with respect to the voltage signal 3a of the reference phase.
In case the voltage detecting signals U, V, W are in normal states, the ROM 3 serves to output the voltage signals 3a, 3b, 3c for keeping the output voltage 5a of the voltage smoothing circuit 5 constant. The voltage signals 3a, 3b, 3c are shifted by 120.degree. with respect to each signal and have iterative values of "1" and "0" at each 90.degree. interval for each phase.
This results in keeping an output pulse signal 6a of the voltage oscillating circuit 6 at a constant frequency pulse and this state means that the voltage detecting signals U, V, W are synchronized with the phase voltage of an a.c. bus. In case an abnormal state takes place in the voltage signals U, V and W at each of 12-divided phase intervals, the phase of each voltage information 3a to 3b is shifted and this results in changing the output voltage 5a of the smoothing circuit 5, thereby entering the output signal 6a of the voltage oscillating circuit 6 into an intermittent oscillating state. That is, the output signal 6a is not made to be a constant frequency pulse.
Actually, if the foregoing PLL feeds a signal synchronized with a phase of the a.c. power source under the control of the microcomputer when controlling the power source, the microcomputer works on the output signal 6a of the voltage oscillating circuit 6 used as a fundamental clock of the microcomputer.
The accuracy of the foregoing power source phase synchronizing apparatus depends on the accuracy of the voltage smoothing circuit 5 and the voltage oscillating circuit 6. In case the supply frequency is shifted by a rate of 10%, the voltage oscillating circuit 6 enters into an intermittent oscillating state, resulting in phase-slipping phenomenon. This phenomenon is brought about especially when the power source led to the a.c. bus is changed from a commercial power source to a non-utility generator.
As will be understood from the above description, if the phase-slipping phenomenon appears in the phase locked loop, an abnormal state takes place in the control of the system using the synchronized signal as a fundamental clock of the microcomputer, resulting in fatal damage to the overall system.
In addition, the peripheral components around the voltage smoothing circuit 5 and the voltage oscillating circuit 6 are composed of analog circuits and this is one of the factors for lowering reliability of the overall system.